1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and in particular, to a semiconductor device including a super junction region and a method of manufacturing the same.
2. Description of the Related Art
Semiconductor devices, such as MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or IGBT (Insulated Gate Bipolar Transistor), which have high-speed switching characteristics and reverse blocking voltage (breakdown voltage) of tens to hundreds V, are widely used for power conversion and control in home electrical appliances, communications devices, automobile motors, and so on. To achieve smaller, higher-efficiency, and lower power consumption power systems using these semiconductor devices, MOSFET and IGBT included in the systems are, for example, required to reduce on-resistance while maintaining high breakdown voltage.
On-resistance of a vertical power MOSFET highly depends on an electrical resistance of its conductive layers (drift layers). In addition, the electrical resistance of the drift layers is determined by the impurity concentration, and smaller on-resistance may be achieved by higher impurity concentration. However, if the impurity concentration becomes higher, then the breakdown voltage in p-n junctions formed between the drift layers and base regions becomes lower. Therefore, the impurity concentration may not be higher than the limit determined depending on the breakdown voltage. Thus, there is a trade-off between the device breakdown voltage and the on-resistance. Improving the trade-off is an important issue for providing semiconductor devices with low power consumption. The trade-off has a limit determined by the device material. Overcoming such limit offers a way to the low on-resistance semiconductor devices.
One example of MOSFET that solves this problem includes a structure where vertically long reed-shaped p-type pillar regions and n-type pillar regions, referred to as a “super junction structure”, are alternately embedded in the drift layers in the lateral direction. The super junction structure creates a pseudo non-doped layer by providing the same amount of charges (impurities) contained in the p-type pillar regions and the n-type pillar regions. It achieves lower on-resistance than the material limit by allowing current flow through the highly doped n-type pillar regions, while maintaining high breakdown voltage.
In off-operation of general semiconductor devices, depletion layers expand from the interfaces of the p-n junctions between p-type base regions and n-type drift layers. The semiconductor devices have such breakdown voltage that is determined by the impurity concentration in the n-type drift layers and the length of depletion layer. On the contrary, in off-operation of the semiconductor device with super junction regions, depletion layers also expand from the interfaces of the p-n junctions between p-type pillar regions and n-type pillar regions in the drift regions. Accordingly, electric field concentration may be reduced near the p-n junction surfaces between the p-type base regions and the n-type drift layers, which may provide larger electric fields in the entire drift regions. Therefore, high breakdown voltage can be obtained even if the n-type pillar regions have higher impurity concentration than the drift regions in the general semiconductor devices. On the other hand, in on-operation of the semiconductor device with super junction regions, the on-resistance may be on the order of five times smaller than that in other semiconductor devices with similar breakdown voltage, because the current flows through the high-concentration n-type pillar regions.
One method of manufacturing a semiconductor device with super junction regions includes the following steps: Firstly, n-type and p-type diffusion regions are selectively formed in a high-resistance epitaxial layer by ion implantation and diffusion, on which an additional high-resistance epitaxial layer is further laminated. Then, as in the lower layer, the step of forming n-type and p-type diffusion regions by ion implantation and diffusion is repeated multiple times. In this manufacturing method, the high-resistance epitaxial layer should be formed with a thickness such that upper n-type/p-type diffusion regions and lower n-type/p-type diffusion regions may be connected to each other.
In the semiconductor device with super junction regions, to achieve further reduction in on-resistance, it is effective to provide a smaller lateral pitch of the super junction regions. This is because providing a smaller pitch may facilitate expansion of depletion layers from the p-n junctions during a non-conduction period, and correspondingly increase the impurity concentration in the pillar regions. That is, to reduce the on-resistance of the semiconductor device, it is necessary to form the pillar regions in the super junction regions with a small width and a high aspect ratio.
In the manufacturing method mentioned above, in order to form a pillar region with a small width and a high aspect ratio, it is necessary to extend the diffusion time or to increase the number of times epitaxial growth and ion implantation steps are performed. In this manufacturing method, if ion implantation and epitaxial growth steps are repeated a larger number of times, then the number of processes correspondingly increase, which results in increased cost. Therefore, the chip area where semiconductor devices are formed must be reduced to mitigate the cost increase.
To reduce the chip area, it is necessary to achieve such low on-resistance characteristics that cannot be achieved by conventional devices, and to increase the usage current density. As can be seen, a reduction in on-resistance of the semiconductor device with the super junction regions can be achieved by pitch refinement of the pillar regions formed in the drift layers of the device region and enhancement of the impurity concentration in the pillar regions.
However, for reducing the cost of the semiconductor device with the super junction regions, reducing the area of the termination region arranged around the device region is a critical issue as well as reducing the area of the device region. The termination region is a part for sustaining high breakdown voltage by extending depletion layers towards the end of the chip where a semiconductor device is formed. It needs to be designed to prevent local electric field concentration upon avalanche breakdown, reliability test, etc. Since the termination region sustains high breakdown voltage, while the device region flows a current upon turn-on operation, the termination region is required to have larger width than the device region. This would pose difficulties in reducing its size.
On the contrary, Japanese Patent Laid-Open No. 2001-298190 discloses a semiconductor device wherein the breakdown voltage of the termination region is enhanced by changing orientations of pillar regions in the termination region, and providing smaller repetition pitch of the pillar regions in the termination region than that in the device region. In order to provide higher breakdown voltage in the termination region, it is necessary, however, that the impurity concentration of the termination region is reduced to facilitate the extension of depletion layers. According to the configuration disclosed in Japanese Patent Laid-Open No. 2001-298190, the impurity concentration increases at the corner part of the termination region since the pillar regions are uniformly provided in the termination region. Thus, it is impossible to prevent breakdown voltage reduction at the termination region, in particular, at the corner part.